能量-動量色散
上述關於能帶結構的內容為了簡化,因此跳過了一個重要的現象,稱為能量的色散(dispersion of energy)。同一個能帶內之所以會有不同能量的量子態,原因是能帶的電子具有不同波向量或者「k-向量」。在[學]]中,k-向量即為粒子的動量,不同的材料會有不同的能量-動量關係(E-k relationship)。
葉青峻guest葉青峻2021/03/10 08:19
能量-動量色散關係式能決定電子或電洞的等效質量(effective mass),以 m ∗ {\displaystyle m^{*}} m^*代表,公式如下:
m ∗ = ℏ 2 ⋅ [ d 2 E ( k ) d k 2 ] − 1 {\displaystyle m^{*}=\hbar ^{2}\cdot \left[{{d^{2}E(k)} \over {dk^{2}}}\right]^{-1}} m^{*} = \hbar^2 \cdot \left[ {{d^2 E(k)} \over {d k^2}} \right]^{-1}
等效質量可視為聯繫量子力學與古典力學的一個參數。這個參數對於半導體材料而言十分重要,例如它和電子或電洞的遷移率(electrons or holes mobility)有高度關聯。電子或電洞的遷移率對於半導體元件的載子傳輸是相當基本的參數。
晶片測試
晶片處理高度有序化的本質增加了對不同處理步驟之間度量方法的需求。晶片測試度量裝置被用於檢驗晶片仍然完好且沒有被前面的處理步驟損壞。如果If the number of dies—the 積體電路s that will eventually become chips—當一塊晶片測量失敗次數超過一個預先設定的閾值時,晶片將被廢棄而非繼續後續的處理製程。
葉青峻guest葉青峻2021/03/10 08:29
晶片測試
晶片處理高度有序化的本質增加了對不同處理步驟之間度量方法的需求。晶片測試度量裝置被用於檢驗晶片仍然完好且沒有被前面的處理步驟損壞。如果If the number of dies—the 積體電路s that will eventually become chips—當一塊晶片測量失敗次數超過一個預先設定的閾值時,晶片將被廢棄而非繼續後續的處理製程。
Device yield or die yield is the number of working chips or dies on a wafer, given in percentage since the number of chips on a wafer (Die per wafer, DPW) can vary depending on the chips' size and the wafer's diameter. Yield degradation is a reduction in yield, which historically was mainly caused by dust particles, however since the 1990s, yield degradation is mainly caused by process variation, the process itself and by the tools used in chip manufacturing, although dust still remains a problem in many older fabs. Dust particles have an increasing effect on yield as feature sizes are shrunk with newer processes. Automation and the use of mini environments inside of production equipment, FOUPs and SMIFs have enabled a reduction in defects caused by dust particles. Device yield must be kept high to reduce the selling price of the working chips since working chips have to pay for those chips that failed, and to reduce the cost of wafer processing. Yield can also be affected by the design and operation of the fab.
Tight control over contaminants and the production process are necessary to increase yield. Contaminants may be chemical contaminants or be dust particles. "Killer defects" are those caused by dust particles that cause complete failure of the device (such as a transistor). There are also harmless defects. A particle needs to be 1/5 the size of a feature to cause a killer defect. So if a feature is 100 nm across, a particle only needs to be 20 nm across to cause a killer defect. Electrostatic electricity can also affect yield adversely. Chemical contaminants or impurities include heavy metals such as Iron, Copper, Nickel, Zinc, Chromium, Gold, Mercury and Silver, alkali metals such as Sodium, Potassium and Lithium, and elements such as Aluminum, Magnesium, Calcium, Chlorine, Sulfur, Carbon, and Fluorine. It is important for those elements to not remain in contact with the silicon, as they could reduce yield. Chemical mixtures may be used to remove those elements from the silicon; different mixtures are effective against different elements.
Several models are used to estimate yield. Those are Murphy's model, Poisson's model, the binomial model, Moore's model and Seeds' model. There is no universal model; a model has to be chosen based on actual yield distribution (the location of defective chips) For example, Murphy's model assumes that yield loss occurs more at the edges of the wafer (non-working chips are concentrated on the edges of the wafer), Poisson's model assumes that defective dies are spread relatively evenly across the wafer, and Seeds's model assumes that defective dies are clustered together.[25]
Smaller dies cost less to produce (since more fit on a wafer, and wafers are processed and priced as a whole), and can help achieve higher yields since smaller dies have a lower chance of having a defect. However, smaller dies require smaller features to achieve the same functions of larger dies or surpass them, and smaller features require reduced process variation and increased purity (reduced contamination) to maintain high yields. Metrology tools are used to inspect the wafers during the production process and predict yield, so wafers predicted to have too many defects may be scrapped to save on processing costs.[26]
葉青峻guest葉青峻2021/03/10 08:39
常見的半導體材料有矽、鍺、砷化鎵等
/
晶片測試
晶片處理高度有序化的本質增加了對不同處理步驟之間度量方法的需求。晶片測試度量裝置被用於檢驗晶片仍然完好且沒有被前面的處理步驟損壞。如果If the number of dies—the 積體電路s that will eventually become chips—當一塊晶片測量失敗次數超過一個預先設定的閾值時,晶片將被廢棄而非繼續後續的處理製程。
/
晶片測試
晶片處理高度有序化的本質增加了對不同處理步驟之間度量方法的需求。晶片測試度量裝置被用於檢驗晶片仍然完好且沒有被前面的處理步驟損壞。如果If the number of dies—the 積體電路s that will eventually become chips—當一塊晶片測量失敗次數超過一個預先設定的閾值時,晶片將被廢棄而非繼續後續的處理製程。
Device yield or die yield is the number of working chips or dies on a wafer, given in percentage since the number of chips on a wafer (Die per wafer, DPW) can vary depending on the chips' size and the wafer's diameter. Yield degradation is a reduction in yield, which historically was mainly caused by dust particles, however since the 1990s, yield degradation is mainly caused by process variation, the process itself and by the tools used in chip manufacturing, although dust still remains a problem in many older fabs. Dust particles have an increasing effect on yield as feature sizes are shrunk with newer processes. Automation and the use of mini environments inside of production equipment, FOUPs and SMIFs have enabled a reduction in defects caused by dust particles. Device yield must be kept high to reduce the selling price of the working chips since working chips have to pay for those chips that failed, and to reduce the cost of wafer processing. Yield can also be affected by the design and operation of the fab.
Tight control over contaminants and the production process are necessary to increase yield. Contaminants may be chemical contaminants or be dust particles. "Killer defects" are those caused by dust particles that cause complete failure of the device (such as a transistor). There are also harmless defects. A particle needs to be 1/5 the size of a feature to cause a killer defect. So if a feature is 100 nm across, a particle only needs to be 20 nm across to cause a killer defect. Electrostatic electricity can also affect yield adversely. Chemical contaminants or impurities include heavy metals such as Iron, Copper, Nickel, Zinc, Chromium, Gold, Mercury and Silver, alkali metals such as Sodium, Potassium and Lithium, and elements such as Aluminum, Magnesium, Calcium, Chlorine, Sulfur, Carbon, and Fluorine. It is important for those elements to not remain in contact with the silicon, as they could reduce yield. Chemical mixtures may be used to remove those elements from the silicon; different mixtures are effective against different elements.
Several models are used to estimate yield. Those are Murphy's model, Poisson's model, the binomial model, Moore's model and Seeds' model. There is no universal model; a model has to be chosen based on actual yield distribution (the location of defective chips) For example, Murphy's model assumes that yield loss occurs more at the edges of the wafer (non-working chips are concentrated on the edges of the wafer), Poisson's model assumes that defective dies are spread relatively evenly across the wafer, and Seeds's model assumes that defective dies are clustered together.[25]
Smaller dies cost less to produce (since more fit on a wafer, and wafers are processed and priced as a whole), and can help achieve higher yields since smaller dies have a lower chance of having a defect. However, smaller dies require smaller features to achieve the same functions of larger dies or surpass them, and smaller features require reduced process variation and increased purity (reduced contamination) to maintain high yields. Metrology tools are used to inspect the wafers during the production process and predict yield, so wafers predicted to have too many defects may be scrapped to save on processing costs.[26]
在107-1學期結束後,本人再度帶領團隊啟程至英方作第二次交流訪問。在兩星期的行程(2018/1/28~2/10)中,除了繼續與主持人Prof. Yeomans及團隊討論交流(圖2(a)),此計畫也參與了Durham University的Senior Lecturer, Dr. Halim Kusumaatmaja以及Northumbria University的Lecturer, Dr. Ciro Semprebon,本人並因此受邀請至Newcastle的Northumbria University於2月2日在Department of Physics and Electrical Engineering講演,講題為On The Impact of Binary Droplets with Identical and Distinct Liquids,與我們和牛津大學的合作主題有密切關連,分別以實驗與數值模擬方法研究異質液滴的碰撞行為與基礎機制。由此二次頻繁與密集的互訪,產出了雙方的進一步連結與初步的計畫成果。
要怎麼訂購呢,價錢多少
可私訊他們粉絲團https://www.facebook.com/tgi.beautycode/posts/1268867986565079
常見的半導體材料有矽、鍺、砷化鎵等
步驟列表
晶片處理
濕洗
平版照相術
光刻Litho
離子移植IMP
蝕刻(干法蝕刻、濕法蝕刻、電漿蝕刻)
熱處理
快速熱退火Annel
熔爐退火
熱氧化
化學氣相沉積 (CVD)
物理氣相沉積 (PVD)
分子束磊晶 (MBE)
電化學沉積 (ECD),見電鍍
化學機械平坦化 (CMP)
IC Assembly and Testing 封裝測試
Wafer Testing 晶片測試
Visual Inspection外觀檢測
Wafer Probing電性測試
FrontEnd 封裝前段
Wafer BackGrinding 晶背研磨
Wafer Mount晶圓附膜
Wafer Sawing晶圓切割
Die attachment上片覆晶
Wire bonding焊線
BackEnd 封裝後段
Molding模壓
Post Mold Cure後固化
De-Junk 去節
Plating 電鍍
Marking 列印
Trimform 成形
Lead Scan 檢腳
Final Test 終測
Electrical Test電性測試
Visual Inspection光學測試
Baking 烘烤
有害材料標誌
許多有毒材料在製造過程中被使用。這些包括:
有毒元素摻雜物比如砷、硼、銻和磷
有毒化合物比如砷化三氫、磷化氫和矽烷
易反應液體、例如過氧化氫、發煙硝酸、硫酸以及氫氟酸
工人直接暴露在這些有毒物質下是致命的。通常IC製造業高度自動化能幫助降低暴露於這一類物品的風險。
Device yield
Device yield or die yield is the number of working chips or dies on a wafer, given in percentage since the number of chips on a wafer (Die per wafer, DPW) can vary depending on the chips' size and the wafer's diameter. Yield degradation is a reduction in yield, which historically was mainly caused by dust particles, however since the 1990s, yield degradation is mainly caused by process variation, the process itself and by the tools used in chip manufacturing, although dust still remains a problem in many older fabs. Dust particles have an increasing effect on yield as feature sizes are shrunk with newer processes. Automation and the use of mini environments inside of production equipment, FOUPs and SMIFs have enabled a reduction in defects caused by dust particles. Device yield must be kept high to reduce the selling price of the working chips since working chips have to pay for those chips that failed, and to reduce the cost of wafer processing. Yield can also be affected by the design and operation of the fab.
Tight control over contaminants and the production process are necessary to increase yield. Contaminants may be chemical contaminants or be dust particles. "Killer defects" are those caused by dust particles that cause complete failure of the device (such as a transistor). There are also harmless defects. A particle needs to be 1/5 the size of a feature to cause a killer defect. So if a feature is 100 nm across, a particle only needs to be 20 nm across to cause a killer defect. Electrostatic electricity can also affect yield adversely. Chemical contaminants or impurities include heavy metals such as Iron, Copper, Nickel, Zinc, Chromium, Gold, Mercury and Silver, alkali metals such as Sodium, Potassium and Lithium, and elements such as Aluminum, Magnesium, Calcium, Chlorine, Sulfur, Carbon, and Fluorine. It is important for those elements to not remain in contact with the silicon, as they could reduce yield. Chemical mixtures may be used to remove those elements from the silicon; different mixtures are effective against different elements.
Several models are used to estimate yield. Those are Murphy's model, Poisson's model, the binomial model, Moore's model and Seeds' model. There is no universal model; a model has to be chosen based on actual yield distribution (the location of defective chips) For example, Murphy's model assumes that yield loss occurs more at the edges of the wafer (non-working chips are concentrated on the edges of the wafer), Poisson's model assumes that defective dies are spread relatively evenly across the wafer, and Seeds's model assumes that defective dies are clustered together.[25]
Smaller dies cost less to produce (since more fit on a wafer, and wafers are processed and priced as a whole), and can help achieve higher yields since smaller dies have a lower chance of having a defect. However, smaller dies require smaller features to achieve the same functions of larger dies or surpass them, and smaller features require reduced process variation and increased purity (reduced contamination) to maintain high yields. Metrology tools are used to inspect the wafers during the production process and predict yield, so wafers predicted to have too many defects may be scrapped to save on processing costs.[26]
常見的半導體材料有矽、鍺、砷化鎵等
/
晶片測試
晶片處理高度有序化的本質增加了對不同處理步驟之間度量方法的需求。晶片測試度量裝置被用於檢驗晶片仍然完好且沒有被前面的處理步驟損壞。如果If the number of dies—the 積體電路s that will eventually become chips—當一塊晶片測量失敗次數超過一個預先設定的閾值時,晶片將被廢棄而非繼續後續的處理製程。
/
晶片測試
晶片處理高度有序化的本質增加了對不同處理步驟之間度量方法的需求。晶片測試度量裝置被用於檢驗晶片仍然完好且沒有被前面的處理步驟損壞。如果If the number of dies—the 積體電路s that will eventually become chips—當一塊晶片測量失敗次數超過一個預先設定的閾值時,晶片將被廢棄而非繼續後續的處理製程。
/
步驟列表
晶片處理
濕洗
平版照相術
光刻Litho
離子移植IMP
蝕刻(干法蝕刻、濕法蝕刻、電漿蝕刻)
熱處理
快速熱退火Annel
熔爐退火
熱氧化
化學氣相沉積 (CVD)
物理氣相沉積 (PVD)
分子束磊晶 (MBE)
電化學沉積 (ECD),見電鍍
化學機械平坦化 (CMP)
IC Assembly and Testing 封裝測試
Wafer Testing 晶片測試
Visual Inspection外觀檢測
Wafer Probing電性測試
FrontEnd 封裝前段
Wafer BackGrinding 晶背研磨
Wafer Mount晶圓附膜
Wafer Sawing晶圓切割
Die attachment上片覆晶
Wire bonding焊線
BackEnd 封裝後段
Molding模壓
Post Mold Cure後固化
De-Junk 去節
Plating 電鍍
Marking 列印
Trimform 成形
Lead Scan 檢腳
Final Test 終測
Electrical Test電性測試
Visual Inspection光學測試
Baking 烘烤
/
有害材料標誌
許多有毒材料在製造過程中被使用。這些包括:
有毒元素摻雜物比如砷、硼、銻和磷
有毒化合物比如砷化三氫、磷化氫和矽烷
易反應液體、例如過氧化氫、發煙硝酸、硫酸以及氫氟酸
工人直接暴露在這些有毒物質下是致命的。通常IC製造業高度自動化能幫助降低暴露於這一類物品的風險。
/
Device yield
Device yield or die yield is the number of working chips or dies on a wafer, given in percentage since the number of chips on a wafer (Die per wafer, DPW) can vary depending on the chips' size and the wafer's diameter. Yield degradation is a reduction in yield, which historically was mainly caused by dust particles, however since the 1990s, yield degradation is mainly caused by process variation, the process itself and by the tools used in chip manufacturing, although dust still remains a problem in many older fabs. Dust particles have an increasing effect on yield as feature sizes are shrunk with newer processes. Automation and the use of mini environments inside of production equipment, FOUPs and SMIFs have enabled a reduction in defects caused by dust particles. Device yield must be kept high to reduce the selling price of the working chips since working chips have to pay for those chips that failed, and to reduce the cost of wafer processing. Yield can also be affected by the design and operation of the fab.
Tight control over contaminants and the production process are necessary to increase yield. Contaminants may be chemical contaminants or be dust particles. "Killer defects" are those caused by dust particles that cause complete failure of the device (such as a transistor). There are also harmless defects. A particle needs to be 1/5 the size of a feature to cause a killer defect. So if a feature is 100 nm across, a particle only needs to be 20 nm across to cause a killer defect. Electrostatic electricity can also affect yield adversely. Chemical contaminants or impurities include heavy metals such as Iron, Copper, Nickel, Zinc, Chromium, Gold, Mercury and Silver, alkali metals such as Sodium, Potassium and Lithium, and elements such as Aluminum, Magnesium, Calcium, Chlorine, Sulfur, Carbon, and Fluorine. It is important for those elements to not remain in contact with the silicon, as they could reduce yield. Chemical mixtures may be used to remove those elements from the silicon; different mixtures are effective against different elements.
Several models are used to estimate yield. Those are Murphy's model, Poisson's model, the binomial model, Moore's model and Seeds' model. There is no universal model; a model has to be chosen based on actual yield distribution (the location of defective chips) For example, Murphy's model assumes that yield loss occurs more at the edges of the wafer (non-working chips are concentrated on the edges of the wafer), Poisson's model assumes that defective dies are spread relatively evenly across the wafer, and Seeds's model assumes that defective dies are clustered together.[25]
Smaller dies cost less to produce (since more fit on a wafer, and wafers are processed and priced as a whole), and can help achieve higher yields since smaller dies have a lower chance of having a defect. However, smaller dies require smaller features to achieve the same functions of larger dies or surpass them, and smaller features require reduced process variation and increased purity (reduced contamination) to maintain high yields. Metrology tools are used to inspect the wafers during the production process and predict yield, so wafers predicted to have too many defects may be scrapped to save on processing costs.[26]
1.█ 圖1 英國牛津大學理論物理系(a)系館及(b)大門
由於此計畫是雙方交換的第一年,為明確雙方共同目標與加強計畫實施之要點與細節,我方至牛津大學拜訪Prof. Julia Yeomans (圖2),並一起於其辦公室網路遠端與Northumbria University的Dr. Ciro Semprebon交換研究心得。其中英方分享利用Lattice Boltzmann法模擬異質液滴碰撞的進度,而我方則展示異質液滴碰撞的實驗成果及利用開放源軟體GERRIS模擬同質液滴正撞比對實驗的成果。
另外在訪問牛津的一個禮拜中,英方博士生Kristian Thijssen在其中一天分享Lattice Boltzmann method原理(圖3 (a))及其如何應用於計算流體力學中,我方則於另一天由碩士生謝宛庭分享如何使用開放源軟體OpenFOAM模擬雙異質液滴碰撞,接著博士生黃冠嶺分享其背後之計算原理並介面追蹤技術(圖3 (b)-(d)),雙方學生在互相學習各自所長,視野可說有顯著的拓展。
█ 第二次臺方訪英學術交流
在107-1學期結束後,本人再度帶領團隊啟程至英方作第二次交流訪問。在兩星期的行程(2018/1/28~2/10)中,除了繼續與主持人Prof. Yeomans及團隊討論交流(圖2(a)),此計畫也參與了Durham University的Senior Lecturer, Dr. Halim Kusumaatmaja以及Northumbria University的Lecturer, Dr. Ciro Semprebon,本人並因此受邀請至Newcastle的Northumbria University於2月2日在Department of Physics and Electrical Engineering講演,講題為On The Impact of Binary Droplets with Identical and Distinct Liquids,與我們和牛津大學的合作主題有密切關連,分別以實驗與數值模擬方法研究異質液滴的碰撞行為與基礎機制。由此二次頻繁與密集的互訪,產出了雙方的進一步連結與初步的計畫成果。
2.唱歌好快樂~快樂王子~湛樂法師沒資格快樂~:XD
台東高中校歌
鯉山挺翠,東海揚濛,巍哉我校立其中。
莘莘學子,濟濟多士聚一堂。
共把科學精研,體魄勤練,四維八德,砥礪發煌。
喜今朝,桃李競秀。願他年,松柏爭蒼。
勇猛精進,日就月將,自強不息,蔚為國光。【祖國清華大學自強不息=附屬台灣區的雄中自強不息】